Phase change memory is a memory device which typically uses a chalcogenide material for the memory elements. A memory element is the unit that actually stores information. In operation, the phase change memory stores information on the memory element by changing the phase of the memory element between amorphous and crystalline phases. The chalcogenide material may exhibit either a crystalline or an amorphous phase, exhibiting a low or high conductivity. Generally, the amorphous phase has a low conductivity (high impedance) and is associated with a reset state (logic zero) and the crystalline phase has a high conductivity (low impedance) and is associated with a set state (logic one). The memory element may be included in a memory cell that also includes a selector, i.e., a select device coupled to the memory element. The select devices are configured to facilitate combining a plurality of memory elements into an array.
Phase change memory elements may be arranged in a cross-point memory array including row address lines and column address lines arranged in a grid. The row address lines and column address lines, called word lines (WLs) and bit lines (BLs), respectively, cross in the formation of the grid and each memory cell is coupled between a WL and a BL where the WL and BL cross (i.e., cross-point). It should be noted that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in cross-point memory.
During a programming operation, the phase of the memory element may be changed by the application of a first bias voltage to the WL and a second bias voltage to the BL resulting in a differential bias voltage across the memory cell that may cause a current to flow in the memory element. The differential bias voltage may be maintained across the memory cell for a first time period sufficient to cause the memory element to “snap back” and then maintained for a second time period to transition the memory element from the amorphous state to the crystalline state or from the crystalline state to the amorphous state. Snap back is a property of the composite memory element that results in an abrupt change in conductivity and an associated abrupt change in the voltage across the memory element.
In a read operation, a target memory cell is selected via the application of a first bias voltage to the WL and a second bias voltage to the BL that cross at the target memory cell for a time interval. A resulting differential bias voltage across the memory element is configured to be greater than a maximum set voltage and less than a minimum reset voltage for the memory element. In response, the target memory element may or may not snap back, depending on whether the memory element is in the crystalline state (set) or the amorphous state (reset). Sense circuitry, coupled to the memory element, is configured to detect the presence or absence of snap back in a sensing time interval. The presence of snap back may then be interpreted as a logic one and the absence of snap back as a logic zero.
Cross-point memory arrays are sensitive to parasitic capacitance including electrode capacitances and capacitive coupling between adjacent conductors (i.e., line to line capacitance), particularly during snap back. Coupling capacitance may exist between a target WL and adjacent WLs or a target BL and adjacent BLs. The abrupt change in voltage (and conductance of the memory element) during snap back can induce relatively high currents through the memory cell from the parasitic capacitances. These currents may result in disturbance or damage to the memory element and may thus shorten the operational life of the memory element and/or memory array.
Prior to a memory access operation, WLs and BLs are typically coupled to nominal bias voltages so that little or no energy is stored in a coupling capacitance. During a memory access operation, a target WL and/or target BL may be decoupled from the nominal bias voltage and coupled to a different, select bias voltage. As the voltage on the selected WL and/or BL transitions to the select bias voltage, a potential difference is produced between the selected WL and adjacent WLs and/or the selected BL and adjacent BLs. Coupling capacitances may begin to charge up (i.e., store energy) in response to this changing potential difference (i=C dv/dt).
When the target WL or BL reaches the select bias voltage, a non-zero voltage exists across the coupling capacitances (e.g., |Vselect bias−Vnominal bias|) and the coupling capacitance stores energy equal to ½ CV2. The potential difference (voltage) across a target memory cell is then the difference between the WL select bias voltage and the BL select bias voltage.
If a snap back event occurs, the impedance of the memory element decreases abruptly and the voltage across the memory cell also decreases abruptly. Current may flow from the coupling capacitors in response to the change in voltage. Since the target WL is coupled to the select bias voltage source and the adjacent WLs are coupled to the nominal bias voltage source, during transients, current from the supply voltage sources will flow in both the target WLs and the adjacent WLs as the sources attempt to maintain their supply voltages at Vselect and Vnominal, respectively. The coupling capacitances may also contribute energy in the form of displacement currents and/or conduction currents. Thus, current through a memory cell includes contributions from energy stored in coupling capacitances, voltage sources and energy associated with electrode capacitance.
Additional capacitance may exist in a signal path between the memory element and the decoding circuitry and/or sensing circuitry. One technique to reduce the disturbance is to disconnect the decoding and sensing circuitry from the target memory element at the time of snap back and to reconnect it after the snap-back event. A drawback of this technique is that the signal generated by the snap back may be degraded after reconnection to the decoding and sensing circuits resulting in unreliable detection of the state of the memory element. Other techniques configured to mitigate the effects of the undesirable capacitive coupling often involve increased component count, reduced efficiency and/or increased circuit complexity.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.